Phase I: Surface Engineering & Physical Vapor Deposition (PVD)
In this initial stage, the silicon wafer is prepared to transition from a raw substrate into a high-conductivity electronic base. This phase is critical because gold’s performance depends entirely on the purity of the environment and the quality of the adhesion.
1. Atomic-Level Substrate Cleaning
Before any deposition occurs, the wafer undergoes a rigorous chemical cleaning process known as RCA Clean or Piranha Etch (a mixture of $H_2SO_4$ and $H_2O_2$). This removes all organic contaminants and metallic impurities at an atomic level.
Equipment Used: Automated Wet Bench / Spin Scrubber
2. The Adhesion Layer (The "Secret" Bridge)
Gold is a noble metal and does not naturally adhere to silicon. To prevent the gold layer from peeling, a very thin "seed" or adhesion layer of Chromium (Cr) or Titanium (Ti) is deposited first, with a thickness of only 5-10 nanometers.
Equipment Used: DC Magnetron Sputtering System
3. High-Vacuum Gold Deposition
The primary gold layer is deposited using E-Beam Evaporation. Inside a high-vacuum chamber ($10^{-7}$ Torr), an electron beam hits a gold crucible, causing the gold to sublimate and condense onto the wafer in a perfectly uniform thin film.
*Note: The gold used must be 5N Grade (99.999% purity) to ensure maximum electrical conductivity for the chip.*
Phase II: Photolithography & Nanoscale Patterning
Once the gold layer is deposited, the next challenge is to carve the intricate "highways" of electricity. This phase defines the chip’s logic and circuit architecture using advanced light-projection technology.
1. Photoresist Spin Coating
The wafer is coated with a light-sensitive polymer called Photoresist. To achieve a perfectly uniform thickness (often less than 1 micron), the wafer is spun at speeds up to 4,000 RPM.
Equipment Used: Precision Spin Coater
2. UV Pattern Projection (The Lithography)
Using a Photomask—which acts as a high-precision stencil—ultraviolet (UV) light is projected onto the wafer. The UV light chemically alters the exposed areas of the photoresist, effectively "printing" the circuit design.
Equipment Used: UV Mask Aligner / Photolithography Stepper
3. The Gold Lift-off Process
Since gold is highly resistant to chemical etching, engineers often use the Lift-off technique. The wafer is submerged in a solvent that dissolves the unexposed photoresist. As the resist dissolves, the gold on top of it "lifts off," leaving behind only the gold that was in direct contact with the substrate.
*Technical Tip: Ultrasonic agitation is essential to ensure clean edges on the gold tracks, preventing short circuits.*
Phase III: Thermosonic Bonding & Quality Assurance
The final stage bridges the gap between the isolated chip and the external electronic system. This is where the functional "interconnects" are established and tested for extreme reliability.
1. Automatic Thermosonic Wire Bonding
To connect the chip to its lead frame, ultra-fine gold wires (ranging from 15 to 25 microns in diameter) are used. The Thermosonic process combines heat, pressure, and ultrasonic energy to fuse the gold wire to the pads without the need for solder, creating an atomic-level bond.
Equipment Used: High-Speed Automatic Wire Bonder
2. Nanometric Inspection (SEM)
Because the circuit features are smaller than the wavelength of visible light, traditional optical microscopes cannot verify the results. We use a Scanning Electron Microscope (SEM) to scan the gold surfaces with a beam of electrons, ensuring there are no micro-cracks or "voids" in the metal.
Equipment Used: SEM - Scanning Electron Microscope
3. Final Hermetic Packaging
The gold-bonded chip is finally sealed in a ceramic or plastic package to protect it from environmental humidity and oxidation. Since gold is chemically inert, these interconnects will remain conductive and corrosion-free for decades.
